The present invention relates to spurious signal suppressing devices, spurious suppressing methods, and fractional-N synthesizers, and particularly relates to a method of and a device for suppressing spurious signals in frequency spectrum output from a fractional-N synthesizer. Further, the present invention relates to a fractional-N synthesizer equipped with a function to suppress such spurious signals.
Recent development of mobile-communication technology and semiconductor manufacturing technology has generated a rapid increase in wide-spread use of personal-handy phones, cordless phones, and the like not only in advanced nations but also in developing countries as well. Technologies required in such mobile-communication field include a PLL-frequency synthesizer.
The PLL-frequency synthesizer has a PLL (phase-locked loop) circuit therein, and controls an oscillator, one of the elements of the PLL circuit, to generate signals of various frequencies. The PLL-frequency synthesizer receives a signal derived from an output of a quartz generator as a reference signal, and changes a frequency of an output signal by a frequency interval equivalent to the cycle of the reference signal.
As the number of mobile, wireless terminals increases rapidly, the number of available channels also needs to be increased in proportion. A frequency space to which channels are allocated, however, is a limited resource, and available frequency bands are allocated on industry-by-industry bases as each industry requires a certain range of frequency space for wireless communication. Against this background, the PLL-frequency synthesizer is required to switch the frequency of an output thereof by a smaller frequency interval with an aim of securing a larger number of channels.
To meet this demand, a fractional-N-frequency synthesizer (or fractional-N synthesizer) has been proposed. In the following, a PLL-frequency synthesizer will be described first with regard to a configuration thereof. Then, a fractional-N-frequency synthesizer of the related art will be explained based on the understanding of the PLL-frequency synthesizer.
FIG. 1 is a block diagram of a PLL-frequency synthesizer generally used in the related art.
As shown in FIG. 1, the PLL-frequency synthesizer includes a phase comparator 1, a charge-pump circuit 2, a loop filter 3, a voltage-control oscillator 4, and a frequency divider 5. The phase comparator 1 detects a phase difference between a signal having a reference frequency fr and a signal having a comparison frequency fp, and outputs a voltage pulse to the charge-pump circuit 2 such that the voltage pulse has a pulse width dependent on the detected phase difference. The charge-pump circuit 2 generates a charge-pump-output current Icp, which has one of the three states, i.e., a flowing-out state, a flowing-in state, and a high-impedance state.
The charge-pump-output current Icp from the charge-pump circuit 2 is smoothed by the loop filter 3, and is converted into a voltage signal which is output from the loop filter 3. The voltage signal output from the loop filter 3. The voltage signal output from the loop filter 3 is supplied to the voltage-control oscillator 4 as a control voltage, so that the voltage-control oscillator 4 generates a signal having a frequency fo depending on the control voltage. The signal having the frequency fo is subjected to N frequency division by the frequency divider 5, and is fed back to the phase comparator 1 as the comparison frequency fp. Here, the reference frequency fr may be generated when a frequency fosc output from a quartz oscillator (not shown) is divided by a frequency divider 6.
The PLL-frequency synthesizer as described above controls the reference frequency fp such that the comparison frequency fp and the reference frequency fr have the same frequency and the same phase. Further, fp is represented as fo/N due to the frequency division by the frequency divider 5. Thus, there is a relation, EQU fo=N.times.fr (1)
The equation (1) means that a step change in the frequency division ratio N entails a step change in fo by a frequency interval equal to the frequency fr. Namely, the PLL-frequency synthesizer is capable of generating various frequencies when only one frequency is supplied from the quartz oscillator.
FIG. 2 is a block diagram of a fractional-N-frequency synthesizer.
As can be seen from the figure, the fractional-N-frequency synthesizer (or fractional-N synthesizer) includes an accumulator 7 and a spurious suppressing circuit 8 newly provided in addition to the configuration of the PLL-frequency synthesizer shown in FIG. 1. The accumulator 7 receives the reference frequency fr from the frequency divider 6 as a clock frequency, and obtains a sum of an accumulated value acm and input data F at each phase-comparison cycle employed by the phase comparator 1. The accumulated value acm of the accumulator 7 is updated with an increment equal to F at each phase-comparison cycle in this manner. In the example of FIG. 2, the accumulator 7 uses the reference frequency fr as a clock frequency thereof. Alternately, the clock frequency maybe the comparison frequency fr or any other frequency signal as long as the frequency thereof corresponds to the phase-comparison cycles of the phase comparator 1.
If the accumulator 7 has an n-bit configuration, an overflow occurs when the accumulated value acm becomes 2.sup.n. When this happens, the accumulator 7 outputs an overflow signal Sov to the frequency divider 5. The frequency divider 5 changes the ratio of frequency division from N to N+1 F times in every 2.sup.n phase-comparison cycles.
FIGS. 3A through 3C are timing charts showing relations between the reference frequency fr, the comparison frequency fp, and the overflow signal Sov. Here, the figures show a case where n=2 and F=1, and either the reference frequency fr or the comparison frequency fp represents the phase-comparison cycles of the phase comparator 1.
For the sake of explanation, the output frequency fo of the voltage-control oscillator 4 is represented as fol when the frequency-division ratio of the frequency divider 5 is N+1, and is denoted as fo2 when the frequency-division ratio is N. In view of the equation (1), the output frequency fo becomes either EQU fol=(N+1).times.fr
or EQU fo2=N.times.fr
wherein the former occurrence takes place F times in 2.sup.n phase-comparison cycles, and the latter occurrence (2.sup.n -F) times. An average of fo can be represented as: ##EQU1##
The equation (2) means that an average of the frequency fo output from the voltage-control oscillator 4 can be changed by a frequency interval smaller than the reference frequency fr when not only N but also F is changed.
A mere addition of the accumulator 7 to the PLL-frequency synthesizer is known to result in "spurious signals" being generated and included in the frequency spectrum of the output of the voltage-control oscillator 4. An average of the output frequency fo of the voltage-control oscillator 4 is represented by the equation (2) as described above. In effect, however, the output frequency fo exhibits periodic swings between fo1 (=(N+1).times.fr) and fo2 (=N.times.fr). such swings generate spurious signals at positions apart from a center frequency by a distance of k.times.(fr/2.sup.n) (k=1, 2, .cndot. .cndot. .cndot.) in the frequency spectrum of the output of the voltage-control oscillator 4.
In order to suppress spurious signals, the fractional-N-frequency synthesizer is provided with th spurious signals suppressing circuit 8. The spurious signal suppressing circuit 8 includes a D/A converter 9, which receives the accumulated value acm of the accumulator 7, and converts it to an electric-current signal so as to supply an output current Iad. The charge-pump-output current Icp from the charge-pump circuit 2 and the output current Iad from eh D/A converter 9 are added together to becomes a current Do, which is then supplied to the loop filter 3. Summation of the currents Icp and Iad serves to suppress the spurious signals.
FIGS. 3D through 3F are timing charts for explaining the principle of the spurious signal suppression. These figures show a case where the accumulator 7 has a 2-bit configuration (i.e., n=2), and the input data F is 1.
The accumulated value acm stored by the accumulator 7 is incremented by I (=F) at each phase-comparison cycle, and returns to zero when overflow is detected. The accumulated value acm, therefore, exhibits changes such as 0, 1, 2, 3, 0, 1, 2, 3, .cndot. .cndot. .cndot.. The accumulator 7 creases overflow once in every four phase-comparison cycles, so that the overflow signal Sov of the accumulator 7 shows changes thereof as shown in FIG. 3C. As a result, the frequency-division ratio of the frequency divider 5 changes from n to N+1 once in every four phase-comparison cycles. In the absence of the spurious signals suppressing circuit 8, the oscillator frequency swings between fo1 (=(N+1).times.fr) and fo2 (=N.times.fr), thereby generating spurious signals in the oscillator output of the voltage-control oscillator 4.
As shown in FIG. 3D, a jitter width tj during which the charge-pump-output current Icp becomes a minimum is widen as accumulation takes place at each phase-comparison cycle, and returns to the narrowest width at the fourth phase-comparison cycle. Changes in the jitter width tj of the charge-pump-output current Icp is associated with the accumulated value acm of the accumulator 7. As shown in FIG. 3E, the output current Iad of the D/A converter 9 used for spurious suppression is designed to have opposite polarizations (plus v.s. minus) to the charge-pump-output current Icp, and, also, is designed to have a current amount, when integrated over time, the same amount as that of the charge-pump-output current Icp, which is achieved by making Iad proportional to the accumulated value acm of the accumulator 7. Because of this, the current Do input to the loop filter 3 has no periodic fluctuations, and, thus, spurious in the output of the voltage-control oscillator 4 is suppressed.
The fractional-N-frequency synthesizer of the related art described above, however, suffers a problem in that the spurious signals in the output of voltage-control oscillator exhibits channel-dependent characteristics. The channel dependency of spurious signals means that a spurious signal-suppression effect by the spurious signal suppressing circuit 8 will be affected when the frequency-division ratio N of the frequency divider 5 is changed to a new ratio with an aim of switching a frequency generated by the fractional-N-frequency synthesizer.
Reasons why such channel dependency is observed in spurious signals will be described below.
The minimum jitter width tj of the charge-pump-output current Icp is represented as: ##EQU2##
If F=1, then, the above equation is reduced to EQU tj=1/fr.times.1/(1+N.times.2.sup.n) (3)
This jitter width tj changes from tj, 2.times.tj, to 3.times.tj as shown in FIG. 3F since a phase difference is accumulated at each phase-comparison cycle. Since the amount of the D/A-converter-output current Iad is the same, when integrated over time, as that of the charge-pump-output current Icp with an aim of canceling the jitter, a width tad of the D/A-converter output should satisfy EQU Icp.times.tj=Iad.times.tad
that is, EQU Iad=(Icp.times.tj)/tad
By substituting the equation (3) for tj, EQU Iad=1/fr.times.1/(1+N.times.2.sup.n).times.Icp/tad (4)
is obtained.
When the frequency-division ratio N of the frequency divider 5 is changed, i.e., when the channel of the frequency synthesizer is changed, as can be seen from the equation (4), the D/A-converter-output current lad is displaced from an optimal current level suitable for suppressing spurious signals, depending on the frequency-division ratio N since fr, n, Icp, and tad are all constant. Because of this, the spurious signals suppressing circuit 8 of the related art could not remove the channel dependency of spurious signals from the fractional-N-frequency synthesizer.
Accordingly, there is a need to prevent the channel dependency of spurious signals in a fractional-N-frequency synthesizer by maintaining a spurius signal-suppression effect even when a frequency-division ratio is changed upon channel switching.